
`timescale 1ns / 1ps

module seq( 
	clk,
	i_cin,
	i_cc,
	i_ccen,
	i_oe,
	i_rld,
	i_data,
	i_instr,
	
	o_full,
	o_en_pl,
	o_en_map,
	o_en_vect,	
	o_data
);

parameter DATA_WIDTH		= 12;
parameter INSTR_WIDTH		= 4;

input clk;
input i_cin;
input i_cc;
input i_ccen;
input i_oe;
input i_rld;


input [DATA_WIDTH-1:0] 	i_data;
input [INSTR_WIDTH-1:0]	i_instr;

output o_full;
output o_en_pl;
output o_en_map;
output o_en_vect;	

output [DATA_WIDTH-1:0] o_data;

wire [DATA_WIDTH-1:0] w_uPC_to_stack;
wire [DATA_WIDTH-1:0] w_stack_to_mux;
wire [DATA_WIDTH-1:0] w_mux_out;
wire [DATA_WIDTH-1:0] w_reg_cnt_to_mux;

wire [1:0]	w_mux_sel;
wire w_mux_clr;
wire [1:0]	w_satck_cmd;
wire [1:0]	w_reg_cnt_cmd;
wire w_reg_cnt_zeo;

stack stack_inst(
	.clk(clk),
	.i_data(w_uPC_to_stack),
	.i_cmd(w_satck_cmd),
	.o_data(w_stack_to_mux),
	.o_full(o_full)
);

reg_cnt reg_cnt_int(
	.clk(clk),
	.i_rld(i_rld),
	.i_cmd(w_reg_cnt_cmd),
	.i_data(i_data),
	.o_data(w_reg_cnt_to_mux),
	.o_zero(w_reg_cnt_zeo)
);

mux1x4 mux1x4_inst(
	.i_sel(w_mux_sel),
	.i_clr(w_mux_clr),
	.i_in0(w_uPC_to_stack),
	.i_in1(i_data),
	.i_in2(w_stack_to_mux),
	.i_in3(w_reg_cnt_to_mux),
	.o_out(w_mux_out)
);

uPC uPC_inst(
	.clk(clk),
	.i_data(w_mux_out),
	.i_cin(i_cin),
	.o_data(w_uPC_to_stack)
);

instr_dec instr_dec_inst(
	.i_instr(i_instr),
	.i_cc(i_cc),
	.i_ccen(i_ccen),
	.i_zero(w_reg_cnt_zeo),
	.o_cmd_reg_cnt(w_reg_cnt_cmd),
	.o_cmd_stack(w_satck_cmd),
	.o_sel_mux(w_mux_sel), 
	.o_clr_mux(w_mux_clr),
	.o_en_pl(o_en_pl),
	.o_en_map(o_en_map),
	.o_en_vect(o_en_vect)	
);

assign o_data = ( i_oe == 1'b1 ) ? w_mux_out : 12'bz;

endmodule
 